Job category: 數位ic設計工程師

Job Contents: Communicate with customers to provide suitable test architecture planning for project scope Working with the APR team to ensure to correct DFT implementation …

Chip Application Front-End Staff ※ Job Contents: Took responsibility of creating SDC for the complex SoC. Took responsibility of timing analysis with customer. Took responsibility …

※ Job Contents: Block/Chip level DFT feature and architecture definition. DFT specification generation and review with customer co-work. Implement block/chip level DC/AC SCAN, …

Job Description: The selected candidate will have to handle RTL design implementation, simulation verification, FPGA verification, Chip integration (floorplan design, package …

Responsibilities: To be discussed in detail during further communication. Qualification: Over 5 years of experience in C++ development Experience in user-space application …

1.VLSI Physical Design 2.Executing floorplanning, design closures on timing, signal integrity, power integrity, DFM as well as physical verifications. 3.Tapeout with multi-million …

1.Tapeout with multi-million gates count SOC design on cutting-edge technologies. 2.Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs. …

Design High speed interface IC.