Job category: 數位ic設計工程師

1.Tapeout with multi-million gates count SOC design on cutting-edge technologies. 2.Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs. …

General Solution Architect / Execution PM ※Job Contents Handle project execution & management for advanced ASIC chip from Netlist-in to GDSII tapeout and silicon bring-up at …

※ Job Contents: Block/Chip level DFT feature and architecture definition. DFT specification generation and review with customer co-work. Implement block/chip level DC/AC SCAN, …

Job Description & Requirement Perform physical synthesis from RTL or gate-to-gate optimization Take responsibility for netlist, SDC and design quality check with customer Chip …

Performs detailed semiconductor account analyses including but not limited to review discussion forum websites and product specifications. Plans, analyzes, and participates in …