Job category: 數位ic設計工程師

Propose design verification plan and do the execution based on IP and system HW architecture/application Develop design verification environment Develop required verification …

Work in PD flow: synthesis, DFT, floorplan, power planning, placement, CTS, routing, timing closure, ECO, IR/EM signoff, and physical verification is a plus. Co-work with physical …

Ability to investigate spec, update testlist, build test case; knowledge of SVA, coverage analysis is plus. Co-work with design verification teams.

Job Description The Axiado Platform Integration Team is looking for an innovative, Systems Engineer, with a passion for learning, to focus on Platform System Integration. The …

Job Description: The selected candidate will have to handle RTL design implementation, simulation verification, FPGA verification, Chip integration (floorplan design, package …

Responsible for industry leading IP Synthesis/Formal/STA. 2 .Responsible for industry leading IP LINT/CDC/VSI. Responsible for industry leading IP regularly regression. …

※ Job Contents: Block/Chip level DFT feature and architecture definition. DFT specification generation and review with customer co-work. Implement block/chip level DC/AC SCAN, …

General Solution Architect / Execution PM ※Job Contents Handle project execution & management for advanced ASIC chip from Netlist-in to GDSII tapeout and silicon bring-up at …