1.Tapeout with multi-million gates count SOC design on cutting-edge technologies. 2.Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs. …
Responsible for Ethernet communication device designs such as Ethernet switch, IoT, RTU, etc by using FPGA main chip. Main scope also include FPGA (such as Xilinx and Intel …
Responsible for Ethernet communication device designs such as Ethernet switch, IoT, RTU, etc by using FPGA main chip. Main scope also include FPGA (such as Xilinx and Intel …