Job category: 數位ic設計工程師

Job Description & Requirement Perform physical synthesis from RTL or gate-to-gate optimization Take responsibility for netlist, SDC and design quality check with customer Chip …

Job Contents: Communicate with customers to provide suitable test architecture planning for project scope Working with the APR team to ensure to correct DFT implementation …

General Solution Architect / Execution PM ※Job Contents Handle project execution & management for advanced ASIC chip from Netlist-in to GDSII tapeout and silicon bring-up at …

Job Description: The selected candidate will have to handle RTL design implementation, simulation verification, FPGA verification, Chip integration (floorplan design, package …

※ Job Contents: Block/Chip level DFT feature and architecture definition. DFT specification generation and review with customer co-work. Implement block/chip level DC/AC SCAN, …

Physical Design Staff ※ Job Contents: Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. Support STA …

Pantherun is a cyber security and data communications company that has designed a One-of-a-kind Chip and software based Intellectual Property for secure Ethernet Communication …

1.Tapeout with multi-million gates count SOC design on cutting-edge technologies. 2.Develop UDSM design methodology for timing/power/reliability/DFM closures and low power designs. …