[PI] PROCESS INTEGRATION ENGINEERING Sr. Manager 製程整合資深經理

As a Sr. manager at Micron Technology, Inc., you will be working with TD/AMD/DFM/CPIE and OMT PI/PEE responsible for cross-tech DRAM technologies Layout/OPC/CMP weakness and process optimizations to improve product quality and reliability, leading and participating in NPI and HVM baseline yield improvement activities, handling new reticle tapeout pre- and -post checks, process margin up, and new defense line setup. This position requires at least 10 years working experience in FE process with 8 years in process integration. Experience and knowledge in Layout edit/GDS view/OPC/DRC/DFM related areas is a plus. Responsibilities and Tasks: • Bridging TD/AMD/Designer with Fab PEE/PI for layout/reticle edit to eliminate process/layout weak points and process margin up.• Reticle edit (revision) sanity check• Cross-fabs baseline issues solution provider• Identity layout weakness and provide counter proposals to TD/AMD• DFM related protocals/BP setup for fabs to follow up• AAL/NUDD/Chop layers sanity checks for NPI Main job will be handling layout/reticle, OPC optimization, DRC error, DFM related issues and innovation. Maximizes yield by working on tools, the process, or wafer fabrication recipe optimization. Troubleshoots wafer fabrication problems and performs root cause analysis through MBPS methodology. Works with other process areas to understand and control process deviations. Collaborate wtih TD/AMD/CMP DFM team/ CPIE for DFM related solutions and fan out to all Micron