Senior Manager Design Verification

Define, manage, and execute design verification strategies for complex semiconductor projects.

Work directly with Taiwanese clients to ensure successful project delivery and long-term partnership growth.

Develop and review test plans.

Develop verification environment/testbench in Module/IP/SOC level.

Develop verification IP and reference model.

Implement test with randomization based coverage driven verification methodology.

Implement functional and functional/code coverage closure.

Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC:

● Low Power verification

● Formal verification