類別: 數位ic設計工程師

これらの求人情報は、参考のために台湾の求人サイトから取得したものです。

情報源 Source: 104
愛爾蘭商益華科技股份有限公司台灣分公司

Product Engineer (Innovus/Genus/Cerebrus)

This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which …
待遇面議
[新竹市 Hsinchu City]
情報源 Source: 104
智原科技股份有限公司

PLL/DLL Design Engineer

General OSC/PLL/DLL/SSCG/CDR design & production experience LC-tank VCO design & production experience CDR design & production experience
待遇面議
[新竹市 Hsinchu City]
情報源 Source: 104
揚毅國際有限公司

FPGA Design Engineer (Hsinchu, Taichung)

Pantherun is a cyber security and data communications company that has designed a One-of-a-kind Chip and software based Intellectual Property for secure Ethernet Communication …
待遇面議
[台中市西區 West District, Taichung City]
情報源 Source: 104
創意電子股份有限公司

G230018-Physical Design Staff/Technical Manager

Physical Design Staff ※ Job Contents: Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. Support STA …
待遇面議
[新竹市 Hsinchu City]
情報源 Source: 104
創意電子股份有限公司

G240056-Execution Project Manager / General Solution Architect (竹科)

General Solution Architect / Execution PM ※Job Contents Handle project execution & management for advanced ASIC chip from Netlist-in to GDSII tapeout and silicon bring-up at …
待遇面議
[新竹市 Hsinchu City]
情報源 Source: 104
創意電子股份有限公司

G240013-Chip Application Front-End Staff/Technical Manager

Chip Application Front-End Staff ※ Job Contents: Took responsibility of creating SDC for the complex SoC. Took responsibility of timing analysis with customer. Took responsibility …
待遇面議
[新竹市 Hsinchu City]
情報源 Source: 104
利明顧問有限公司

Senior Analyst (English Native Speaker)

Performs detailed semiconductor account analyses including but not limited to review discussion forum websites and product specifications. Plans, analyzes, and participates in …
待遇面議
[台北市大安區 Daan District, Taipei City]
情報源 Source: 104
創意電子股份有限公司

G240009-DFT Technical Manager/Sr. Engineer

※ Job Contents: Block/Chip level DFT feature and architecture definition. DFT specification generation and review with customer co-work. Implement block/chip level DC/AC SCAN, …
待遇面議
[新竹市 Hsinchu City]