G240006-Chip Application Front-End Senior Engineer

Job Description & Requirement Perform physical synthesis from RTL or gate-to-gate optimization Take responsibility for netlist, SDC and design quality check with customer Chip I/O arrangement and verification with in-house tool Perform low power structure verification (UPF/CPF) Perform power replay and power analysis Review/check implementation quality in each design stage Cooperate with P&R in timing analysis Planning chip level STA (e.g. flatten, HyperScale) strategy and machine arrangement for big design Perform MMMC timing closure and signoff check Schedule and team resource management 5 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus