Chiplet Integration Process Engineer, up to Sr. Staff (Hsinchu)(3069886)

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表:https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/Chiplet-Integration-Process-Engineer–up-to-Sr-Staff_3069886 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/Chiplet-Integration-Process-Engineer--up-to-Sr-Staff_3069886 【Overview】 As a leading technology innovator, Qualcomm pushes the boundaries of what’s possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. 【Job Description】 Drive Process Technology evaluation, development and execution for Qualcomm’s multi-chip integration through advanced bonding and interconnect technologies. Candidate will help define, evaluate, and develop diverse chiplet integration schemes using advanced bonding techniques utilizing appropriate interconnect schemes. Candidate will collaborate with Qualcomm internal and Foundry teams, including Design and Package teams, to develop and propagate these Chiplet solutions while meeting key product specifications. Candidate must possess expert knowledge of advanced process technology details driving industry-wide chiplet integration schemes including Wafer-on-Wafer bonding, Chip-on-Wafer 3D Bonding, Hybrid Cu[1]Cu Bonding. Experience in Chiplet integration schemes and related thermal, electrical, and mechanical trade-offs is a requirement. Good communication skills as well as the ability to work in a geographically diverse team environment are essential. 【Basic Qualifications】 • 5yrs of experience in evaluating and developing multi-chip integration schemes through advanced bonding technologies. 【Preferred Qualifications】 • RTL to GDS design flow and EDA Tool dependencies 3DIC Design Flows Experience in Mentor / Cadence tools for layout generation. • Key Words 3DIC, Hybrid Bonding, Wafer-on-Wafer Bonding, WoW Bonding, Chiplets, Cu Bonding, TSV