G240013-Chip Application Front-End Staff/Technical Manager
Chip Application Front-End Staff ※ Job Contents:
- Took responsibility of creating SDC for the complex SoC.
- Took responsibility of timing analysis with customer.
- Took responsibility of planning low-power structure and review flow (CPF/UPF).
- Supported back-end team in post-layout timing closures
- Supported project team in central tech-library management
- Run EDA-Tool and GUC in-house design kit. ※ Requirements:
- Familiar with ASIC Flow.
- Understood SoC IO structure and experienced of integrating 3rd party IP.
- Understood physical synthesis flow.
- 3 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus
Chip Application Front-End Manager/Technical Manager
- Perform physical synthesis from RTL or gate-to-gate optimization
- Take responsibility for netlist, SDC and design quality check with customer
- Chip I/O arrangement and verification with in-house tool
- Perform low power structure verification (UPF/CPF)
- Perform power replay and power analysis
- Review/check implementation quality in each design stage
- Cooperate with P&R in timing analysis
- Planning chip level STA (e.g. flatten, HyperScale) strategy and machine arrangement for big design
- Perform MMMC timing closure and signoff check
- Schedule and team resource management
- 7 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus